In testing of modern-day semiconductor chips it is in some cases necessary to contact well over 1000 signal pins. This problem can only be mastered at chip and wafer level by very complex and costly contactors.
In fault analysis of defective chips taken from a so-called multi-chip carrier, the additional problem arises of re-attaching a single chip of this kind to the tester; that is, the chip-C4 contacts must be restored in order then to be able to position and solder the tested chip on a chip carrier. Only then can the test be carried out on the test system.
In test procedures of this kind the chips under test are mounted on an associated chip carrier (substrate), on which the chips are fixed in position for testing. The substrate bears appropriate contact points (pads) which, after the chip has been pressed on to the substrate, are electrically connected to the contacts of the chip.
One possibility of forming the electrical contacts of the chip is by the so-called controlled collapse chip connections (C4). In this mode of contacting all electrical connections of the chip (signals and power supply) on the active chip side are routed to the surface of the chip and each fitted with one C4 pad (consisting of PbSn pellets). When the chip has been positioned on the substrate the chip is soldered together with the substrate in a continuous furnace; that is, the chip C4 pads are fused and soldered to the corresponding substrate pad.
In view of the large number of contact elements nowadays found on a single chip, it is very important to align the chips under test precisely on the substrate. In this regard it should be noted that such precise alignment of C4 chips of this kind is not possible using the edge of the chip, as the saw gap (wafer dicing) exhibits too high tolerances.